Method and apparatus for reducing hardware scan dump data
US6832342B2 · kind B2 · utility
9Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2001 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer implemented instructions for processing an error in a multiprocessor data processing system. An error is detected within the data processing system. A chip, causing the error, is identified within a plurality of chips to form an identified chip. Data is collected from the identified chip and hardware associated with the identified chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.