Semiconductor integrated circuit device
US6833750B2 · kind B2 · utility
6Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/146
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit and power control method use one of a supply voltage of the circuit and a delay time of the circuit to control a substrate bias voltage applied to a substrate of an insulated gate field effect transistor. High speed operation, consuming a small amount of power, is achieved. A CMOS circuit has a widened operating voltage range, with reduced leak currents in a standby mode in a range of high supply voltage, reducing power consumption of the CMOS circuit, and increasing operating speed of the CMOS circuit in the range of low supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.