Frame buffer organization and reordering
US6833834B2 · kind B2 · utility
6Cited by
7References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2001 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Jun 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.