Semiconductor memory device having redundancy system
US6834016B2 · kind B2 · utility
9Cited by
8References
9Claims
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Assignee
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Key dates
| Filing date | Apr 23, 2003 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Apr 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/787
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.