Semiconductor memory having memory cells requiring refresh operation
US6834021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Feb 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation control circuit sets an inactivating timing of sense amplifiers activated in response to a read request, a write request, or a refresh request, to the timing a maximum possible quantity of signals which can be output from the sense amplifiers operating in response to the refresh request is transmitted to memory cells. Tailoring the activating period of the sense amplifiers to a refresh operation can reduce access time. A refresh control circuit generates a predetermined number of refresh requests consecutively to refresh all of the memory cells before extending the cycle of generating refresh requests. When refresh requests occur consecutively, the refresh frequency can be lowered to reduce power consumption. As a result, access time can be reduced without increasing power consumption during the standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.