Bidirectional bus repeater for communications on a chip
US6834318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Apr 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled. Thereafter, the opposite bus segment (bus-B) is driven by the repeater buffers, until the bus segment bus-B reaches the same logic level as the bus segment bus-A. The logic leve…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.