Nonvolatile semiconductor memory device having plural memory circuits selectively controlled by a master chip enable terminal or an input command and outputting a pass/fail result
US6834322B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2000 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Jan 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device capable of controlling a single memory chip similar to a plurality of memory chips. The memory chip has a plurality of Electrically Erasable Programmable Read Only Memory circuits, each of which includes a control circuit for carrying out sequential writing control and which EEPROM circuits share a data bus. Each of the EEPROM circuits has a Chip Enable terminal CE and a Ready/Busy terminal RIB, so that data writing processes can be simultaneously carried out in the respective EEPROM circuits in parallel. The activity and inactivity of each of the EEPROM circuits may also be controlled by a logical combination of a master chip enable signal and a chip enable signal of each of the individual EEPROM circuits. A pass or fail result of writing operations may be output or held and accumulated, with the nonvolatile semiconductor memory device having modes of operation in which it is determined whether data may be input to a data buffer by selectively referring to a pass/fail result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.