Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US6834323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2000 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Jul 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. A host processor verifies external to the memory the programming of the plurality of data words into the memory. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.