Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition
US6834338B1 · kind B1 · utility
6Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.