Low temperature polysilicon thin film transistor and method of forming polysilicon layer of same
US6835606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2003 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Aug 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6715
Abstract
A low temperature polysilicon thin film transistor and a method of forming the polysilicon layer inside the thin film transistor. An amorphous silicon layer is formed over a panel. The panel has a display region and a peripheral circuit region. A metallic layer is formed over a portion of the amorphous silicon layer in the peripheral circuit region. A crystallization process is performed to transform the amorphous silicon layer in the peripheral circuit region into a polysilicon layer. Thereafter, an excimer laser annealing process is performed to increase the grain size of the polysilicon layer in the peripheral circuit region and, at the same time, transform the amorphous silicon layer in the display region into a polysilicon layer. Since the average grain size of the polysilicon layer in the peripheral circuit region is larger, electron mobility is increased as demanded. Similarly, since the average grain size of the polysilicon layer in the display region is smaller, leakage current is decreased as demanded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.