Signal sampling method and circuit for improved hold mode isolation
US6836158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2003 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Aug 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.