Chireix architecture using low impedance amplifiers
US6836183B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2002 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Oct 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/21157
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for use in amplifying amplitude and phase modulated signals. A circuit uses a combiner with dual parallel signal amplifiers feeding it. The signal amplifiers have a low output impedance while the combiner does not provide any isolation between its inputs from the signal amplifiers. As in other Chireix architectures, the signals from the signal amplifiers are phase modulated prior to being fed to the combiner. The combiner then combines these two signals and, depending on how these two signals are combined, the resulting output of the combiner is amplitude modulated. The signal amplifiers may be Class D or Class F amplifiers to provide high efficiency amplification of the signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.