Method and apparatus for reducing power consumption in a cache memory system
US6836824B1 · kind B1 · utility
14Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.