Peripheral device interface chip cache and data synchronization method
US6836829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2001 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Oct 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/303
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The cache system and data synchronization method can be applied to the peripheral device interface control chip having a data buffer and a peripheral device interface controller. The data buffer is located inside the control chip for holding data stream read from a memory unit so that data required by the peripheral device is provided. When the data stream is still valid, the data stream is retained. The peripheral device interface controller is installed inside the control chip. The peripheral device interface controller detects if the data stream inside the data buffer includes the data required by the peripheral device and whether the data stream is still valid or not. The peripheral device interface controller also controls the placement of the data stream retrieved from the memory into the data buffer and state transition of the data buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.