Efficient memory allocation scheme for data collection
US6836861B2 · kind B2 · utility
2Cited by
2References
21Claims
0Family size
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Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/348
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory is already in use by other system functions, utilizing such unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.