CMOS image sensor arrangement with reduced pixel light shadowing

US6838715B1 · kind B1 · utility

Assignee

• ESS TECH, INC. · US

Inventors

• Selim Bencuya · Irvine, US
• Richard Mann · Santa Clara, US
• Erik Stauber · San Diego, US

Key dates

• Filing date: Apr 29, 2003
• Grant date: Jan 4, 2005
• Expiry date: May 24, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/929

Abstract

An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.