Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
US6838899B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Feb 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).The present system also comprises a method for correcting errors in a programmable logic device having configuration data to program the programmable logic device. The method comprises a background reading of the configuration data. Next, the configuration data is analyzed for errors. Finally, the configuration data is then corrected and the configuration data is rewritten if errors are located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.