Level translator for high voltage digital CMOS process
US6838905B1 · kind B1 · utility
72Cited by
10References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 15, 2002 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Oct 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The speed of a level shifter is increased by utilizing an additional transistor to pull down the voltage on a first intermediate node, and an additional transistor to pull down the voltage on a second intermediate node. In addition, a precharge circuit is utilized to precharge the voltage on the first and second intermediate nodes to further increase the speed of the level shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.