Analog-to-digital converter methods and structures for interleavably processing data signals and calibration signals
US6839009B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jul 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and structures are provided for the interleaved calibration and subsequent correction of errors in switched-capacitor converter stages of pipelined analog-to-digital converters. The interleaved calibration can be run continuously or at selected times without disturbing the ongoing processing of input data signals. With first and second sets of capacitors, converter stages interleavably process input data signals and input calibration signals. Once these stages have been calibrated with their second sets of capacitors, the first and second sets are exchanged and the converter stages subsequently process input data signals with their second sets of capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.