PFC-PWM controller having a power saving means
US6839247B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A PFC-PWM controller with a power saving means is disclosed. A built-in current synthesizer generates a bias current in response to feedback voltages sampled from the PWM circuit and the PFC circuit. The bias current modulates the oscillation frequency to further reduce the switching frequencies of the PWM signal and the PFC signal under light-load and zero-load conditions. Thus, power consumption is greatly reduced. The PFC and the PWM switching signals interleave each other, so that power can be transferred more smoothly from the PFC circuit to the PWM circuit. The saturation of the switching components can be avoided by limiting the maximum on-time of the PWM signal. Further, an external resistor is used to start up the PFC-PWM controller and provide an AC template signal for PFC control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.