Semiconductor device having different types of memory cell arrays stacked in a vertical direction
US6839260B2 · kind B2 · utility
82Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Oct 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor memory device capable of fast rewriting with a small area, and/or large-capacity operation with a small area or fast operation and low power consumption operation, peripheral circuits such as logic circuit, buffer memory and sense circuit or part thereof are formed on a semiconductor substrate surface, and memory cells are provided thereon with an insulator film interposed therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.