Digital quadrature demodulation and decimation without multipliers
US6839389B2 · kind B2 · utility
16Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Mar 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/707
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.