Efficient complex multiplication and fast fourier transform (FFT) implementation on the manarray architecture
US6839728B2 · kind B2 · utility
35Cited by
18References
19Claims
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Key dates
| Filing date | Jun 22, 1999 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jun 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
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