Computer architecture with caching of history counters for dynamic page placement
US6839739B2 · kind B2 · utility
12Cited by
10References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 9, 1999 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Sep 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system using distributed memory is provided with a cache of history counters located within each memory controller. Each entry of the cache of history counters represents one page in memory that has the potential to increase system performance by migrating or replicating to other memory locations. The cache of history counters permits creating histories of local memory accesses by remote processors for purposes of dynamic page placement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.