Method and circuit for reliable data capture in the presence of bus-master changeovers
US6839856B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture. The method includes: providing an N-stage latch including a first stage latch and a second stage latch, wherein N is two or larger; loading every Nth word of a data stream into the first stage latch using a first signal based on a strobe passed in the data stream; loading every N+1st word of the data stream into the second stage latch using a second signal based on the strobe passed in the data stream; unloading every Nth word from the first stage latch using a third signal based on an internal bus c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.