Semiconductor integrated circuit having clock synchronous type circuit and clock non-synchronous type circuit
US6839859B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jun 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.