Capture clock generator using master and slave delay locked loops
US6839860B2 · kind B2 · utility
43Cited by
21References
43Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jan 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator comprising a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.