Method for processing an electronic system subjected to transient error constraints and memory access monitoring device
US6839868B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1999 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Oct 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to a processing procedure for an electronic system subject to transient error constraints, in which two virtual sequences installed on a single physical sequence are multiplexed in time in one given real time cycle (the data resulting from each execution of a virtual sequence being stored so that they can be voted before use), and in which if an error is detected, the real time cycle in progress is inhibited and a healthy context is reloaded to make a restart that consists of a nominal execution of the next cycle starting from the reloaded context.This invention also relates to a memory access monitoring device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.