Error-correcting code interleaver
US6839870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Mar 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/276
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Memory may be partitioned into ever-sliding FIFOs. Each of the FIFOs may be stacked end-to-end in memory with the oldest data at the base offset and the newest at the end (or vice-virsa). Each symbol, the pointer may be incremented (modulo the set size) by an appropriate amount (typically J more than for the previous symbol). After each set, the pointers may be incremented by J more than the previous increment and the process starts over, wrapping around the memory if the end of the memory is reached. After a preset number of symbols, the process may restart from an increment of J. Alternatively, the pointers may be decremented rather than incremented. Thus, the newest symbol cannibalizes the memory position vacated by the oldest symbol in the current FIFO, causing the FIFOs to “slide”, providing for a very efficient and reliable use of memory for error-correcting code interleaving.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.