Method and apparatus for design of integrated circuits
US6839882B2 · kind B2 · utility
5Cited by
24References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.