Method of fabricating a COF utilizing a tapered IC chip and chip mounting hole
US6841419B2 · kind B2 · utility
26Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | May 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a COF package comprises the steps of providing a resin film substrate with a hole for receiving a chip, providing an IC chip having electrodes, inserting the IC chip into the hole so as to fix it with its electrodes exposed above the substrate surface, and forming a circuit pattern on the substrate surface for connection with the electrodes. The hole and the IC chip are tapered, and the IC chip is secured in the hole with sealant or adhesive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.