Method of fabricating semiconductor device having alignment mark
US6841451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Feb 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of fabricating a semiconductor device capable of remarkably reducing the quantity of misalignment after an etching step is obtained. This method of fabricating a semiconductor device comprises a first lithography step of transferring a mask pattern onto a first semiconductor substrate as a first resist pattern with positional reference to a first alignment mark, a first etching step of performing etching through the first resist pattern serving as a mask, a step of measuring the quantity of misalignment after the first etching step and a second lithography step of thereafter transferring the mask pattern onto a second semiconductor substrate as a second resist pattern while correcting the positional reference based on the first alignment mark on the basis of the quantity of misalignment after the first etching step. Thus, the positional reference in the second lithography step can be previously corrected to eliminate the quantity of misalignment after the etching step, whereby the quantity of misalignment after the second etching step is remarkably reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.