Power gain reduction circuit for power amplifiers
US6842072B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | May 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a gain reduction circuit comprises a first terminal, where the first terminal is coupled to a control signal. The gain reduction circuit further comprises a second terminal, where the second terminal is coupled to an input of an amplifier, and where the amplifier is configured to operate in low-power mode and high-power mode. The gain reduction circuit further comprises a transistor coupled to the first terminal and the second terminal. The transistor can be, for example, a bipolar transistor, such as an NPN GaAs heterojunction bipolar transistor, having a base, a collector, and an emitter, where the base being is coupled the control signal, the collector is coupled to the input of the amplifier, and the emitter is coupled to ground. According to this exemplary embodiment, the transistor causes a gain of the amplifier to be reduced when the amplifier is operating in low-power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.