Low-jitter clock distribution circuit
US6842136B1 · kind B1 · utility
5Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Nov 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-jitter clock distribution circuit, used in an integrated circuit having multiple analog-to-digital converters (ADCs), includes a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor. The ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter is equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by the semiconductor fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.