Semiconductor memory of a dynamic random access memory (DRAM) type having a static random access memory (SRAM) interface
US6842391B2 · kind B2 · utility
19Cited by
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6Claims
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Key dates
| Filing date | Sep 5, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Sep 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.