Low latency buffer control system and method
US6842831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Dec 28, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.