Method and apparatus for a burst write in a shared bus architecture
US6842837B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2001 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Aug 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.