Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay
US6842851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Jul 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.