METHOD PROGRAMMABLE LOGIC DEVICE, INFORMATION PROCESSING SYSTEM AND METHOD OF RECONFIGURING CIRCUIT FOR SEQUENTIALLY PROCESSING DATA IN BLOCKS AND TEMPORARILY STORING DATA PROCESSED UNTIL NEXT CONFIGURATION
US6842854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Aug 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a method of implementing cache logic technique in which total data processing time can be reduced, input data divided into block is sequentially processed in units of block in plural circuits using a programmable logic device provided with a circuit information input controller, a programmable logic circuit sector and a data cache. The plural circuits are sequentially reconfigured in the programmable logic device and execute processing per plural blocks which can be stored in the data cache. Intermediate data in units of plural blocks is stored in the data cache to be input data to a reconfigured circuit and intermediate data as the result of the processing by the reconfigured circuit is overwritten to the data cache. When the processing of the plural circuits is finished, the result of the processing is output to an external device without being stored in the data cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.