Dielectric layer for semiconductor device and method of manufacturing the same
US6844604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2001 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.