Dynamic method for limiting the reverse base-emitter voltage
US6844768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2003 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Jul 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/72
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from μ-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages. A circuit having an input voltage connected thereto through a finite impedance may comprise: a transistor having a base, a collector and an emitter; a comparator having a comparator output and having an input connected between the base and the input voltage; a clamping circuit having an output connected to the base and an inpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.