Threshold voltage extraction circuit
US6844772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A third, MOS transistor having a source and a gate, and a resistor circuit, together adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, are coupled to the second transistor and to the first input of the holding circuit. A fourth, MOS transistor coupled to the first transistor and to the second input of the subtracting circuit through a second resistor circuit is adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit. A second current mirror coupled to the first current mirror is adapted to cause a current to flow through a third resistor circuit that corresponds to the current through the first current mirror to thereby provide an output voltage corresponding to the threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.