Co-prime division prescaler and frequency synthesizer
US6845139B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Mar 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/193
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.