Analog peak detection circuitry for radio receivers
US6845232B2 · kind B2 · utility
76Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 3, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Jul 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/3052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors that are introduced by crystals within filters and other devices. A voltage follower and a current mirror in which a MOSFET coupled to an output node produces a voltage across its gate to source terminals whose value is a function of a sum of the gate to source voltages of two MOSFET devices that receive a logarithm of an I modulated channel and a logarithm of a Q modulated channel, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.