Multi-port cache memory
US6845429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2001 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Apr 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The conventional multi-port cache memory, which is formed by using multi-port cells, is excellent in its operating speed. However, the integration area of the constituent multi-port cells is increased in proportion to the square of the number of ports. Thus, if it is intended to decrease the cache miss probability by increasing the storage capacity, the chip size is increased correspondingly, which increases the manufacturing cost. On the other hand, the multi-port cache memory of the present invention is formed by using, as constituents, one-port cell blocks adapted for a large storage capacity, making it possible to easily provide a multi-port cache memory of a large storage capacity and reduced integration area, which has a large random access bandwidth, is capable of parallel access from a plurality of ports, and is adapted for use in advanced microprocessors having a small cache miss probability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.