High-speed bus with embedded clock signals
US6845461B1 · kind B1 · utility
16Cited by
5References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4278
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.