Memory sub-system error cleansing
US6845472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or cleansing operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the cleansing logic initiates a cleansing routine in response to an event such as an operator instruction or a periodic schedule. By implementing the cleansing operation, the system does not rely on external READ commands to verify data integrity. Further, a monitoring device is coupled between the cleansing logic and a memory scheduler. The monitoring device provides a feed back mechanism from which to vary the frequency of certain memory requests such as the cleansing and scrubbing operations. The cleansing routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the cleansing routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.