Emitter coupled logic circuit with a data reload function
US6847233B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An emitter coupled logic circuit with a data reload function is disclosed. The emitter coupled logic (ECL) circuit includes first and second in series transistors consisting of bipolar junction transistors (BJTs) and field effect transistors (FETs), respectively. The bipolar junction transistor receives a reload signal, and the field effect transistor receives a reload data. Therefore, using the serial control of the bipolar junction transistors together with the field effect transistors, the digital reload data may be reloaded into the ECL circuit. Since the invention utilizes the field effect transistors to directly receive and set the reload data, it is not necessary to pre-convert the digital reload data into a front-stage ECL voltage level. In addition, because the reload data can be sent to the field effect transistors before the reload signal enables, the field effect transistors may be set to ON or OFF in advance. Consequently, as soon as the reload signal RL is enabled, the states of the output terminals may be controlled according to the reload data so as to speed up the data reload operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.