Variable duty cycle clock generation circuits and methods and systems using the same
US6847244B2 · kind B2 · utility
15Cited by
5References
10Claims
0Family size
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Key dates
| Filing date | Jul 22, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jul 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.