Symmetric line coding
US6847312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Oct 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method an apparatus for symmetric line coding is provided where a binary input signal d is received; a value for each of a pair of binary bits p and q are dynamically defined in response to the input stream; and a pair of output bitstreams v1 and v2 are dynamically generated in accordance with the following: if d=1, then v1=p and v2=p, and if d=0, then v1=(1−q) and v2=q.In illustrative embodiments of the invention, the generation may be performed by symmetric-line coding machines, including: a bitstream symmetric line coding machine, a regular bitstream symmetric line coding machine, a complementary regular bitstream symmetric line coding machine, a binary complementary regular symmetric line coding machine, a bitstream parallel symmetric line coding machine, a regular bitstream parallel symmetric line coding machine, a complementary regular bitstream parallel symmetric line coding machine, and a binary complementary regular parallel symmetric line coding machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.